17 lines
240 B
VHDL
17 lines
240 B
VHDL
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entity e is
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end entity e;
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library std;
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use std.textio.all;
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architecture e of e is
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begin
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ee:
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process is
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variable eee : line;
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begin
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write(eee, string'("e"));
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writeline(output, eee);
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end process ee;
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end architecture e;
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